| Precision | Peak (PFLOPS) | Per GPU (TFLOPS) | TFLOPS/W |
|---|---|---|---|
| BF16 | 50.4 | 197.0 | — |
| INT8 | 100.6 | 393.0 | — |
All figures are dense. Vendors commonly headline the sparse number, which is twice the dense one.
2D torus ICI, 400 GBps bidirectional per chip
A full TPU v5e pod is 256 chips in a 2D torus. Per chip Google publishes 197 TFLOPS bf16 and 393 TOPS int8, giving 50.4 PFLOPS and 100.6 POPS across the pod. Memory is 256 x 16 GB HBM at 800 GiBps per chip, with 400 GBps of bidirectional inter-chip interconnect per chip. v5e is Google's cost-and-efficiency oriented generation, which is why its pod is a thirty-fifth the size of the v5p pod launched alongside it. Google publishes no pod-level compute or power figure; the compute above is chip count times published per-chip peak, the convention Google's own published v4 and Ironwood pod figures both confirm. No sparse figures are published, so all figures are dense.