| Precision | Peak (PFLOPS) | Per GPU (TFLOPS) | TFLOPS/W |
|---|---|---|---|
| FP64 | 2.40 | 33 | — |
| FP32 | 9.36 | 130 | — |
| TF32 | 144 | 2,000 | — |
| FP16 | 288 | 4,000 | — |
| BF16 | 288 | 4,000 | — |
| FP8 | 1,260 | 17,500 | — |
| INT8 | 18.0 | 250 | — |
| NVFP4 | 2,520 | 35,000 | — |
| FP6 | 1,260 | 17,500 | — |
| FP32_TC | 28.8 | 400 | — |
| FP64_TC | 14.4 | 200 | — |
All figures are dense. Vendors commonly headline the sparse number, which is twice the dense one.
NVLink 6 / NVSwitch
Rack-scale system pairing 72 Rubin GPUs with 36 Vera CPUs (3,168 Olympus Arm cores total, 54 TB LPDDR5X CPU memory). Headline NVFP4 inference 3,600 PFLOPS dense; NVFP4 training 2,520 PFLOPS dense. Tensor-core-emulated FP32 SGEMM reaches 28.8 PFLOPS, FP64 DGEMM 14.4 PFLOPS. Aggregate memory shown is HBM4 only (CPU LPDDR5X is excluded from GPU memory aggregate). Total chips per rack: 1,296. Specifications preliminary per NVIDIA GTC 2025 footnote.