Biren BR100

The Biren (壁仞科技) BR100 is a dual-die MCM GPGPU (V-core SIMT + T-core matrix) on TSMC 7nm (1074 mm2, 77B transistors), unveiled at Hot Chips 34 in August 2022. Stored figures are Biren's launch "Peak Performance" claims — published as a single column with NO sparsity qualifier, read here as dense: 256 TFLOPS FP32, 512 TFLOPS TF32+ (Biren's 24-bit E8M15 type), 1024 TFLOPS BF16, and 2048 TOPS INT8. These were never independently benchmarked, hence vendor_claimed. Memory is 64 GB HBM2E (official slide) with BLink scale-up at 2.3 TB/s; the ~1.6 TB/s memory bandwidth is a third-party (Chips and Cheese) estimate, not a Biren figure. FP16 has no separately published peak (likely shares the BF16 path) and is omitted; the BR100 has no FP8 and no FP64 datapath.