Microsoft Maia 200 NEW
Overview
Microsoft Maia 200 is Microsoft's second-generation in-house AI accelerator and its first purpose-built for inference, announced and deployed on 26 January 2026. Each chip is fabricated on TSMC's 3nm process with over 140 billion transistors inside a 750W SoC TDP envelope, and pairs 216GB of HBM3e at 7 TB/s with 272MB of software-managed on-die SRAM split between cluster-level and tile-level pools. Microsoft publishes 10.1 PetaOPS of FP4 and states that FP4 throughput is twice FP8 and eight times BF16, which places FP8 at roughly 5.05 PFLOPS. Compute is arranged as tiles, each combining a Tile Tensor Unit for FP8, FP6 and FP4 matrix multiplication with a Tile Vector Processor covering FP8, BF16, FP16 and FP32, grouped into clusters around shared SRAM and a multi-level DMA subsystem. Scale-up runs over standard Ethernet rather than a proprietary fabric: an on-die NIC delivers 2.8 TB/s of bidirectional bandwidth, four accelerators per tray are directly connected in a switchless Fully Connected Quad, and a switched second tier reaches 6,144 accelerators. Microsoft claims 30 percent better performance per dollar than the newest hardware already in its fleet, three times the FP4 throughput of AWS Trainium3, and FP8 throughput above Google's TPU v7. Maia 200 is deployed first in the US Central region near Des Moines, Iowa, with US West 3 near Phoenix, Arizona to follow, serving OpenAI GPT-5.2 models, Microsoft Foundry and Microsoft 365 Copilot. It is captive Azure silicon and is not sold or rented as hardware. Microsoft states no dense or sparse basis for any of these figures and describes no structured-sparsity hardware, so the basis is not stated; the values are recorded as peak throughput with no sparse counterpart.
Performance Metrics
Peak theoretical throughput by precision type
| Precision | Bits | Peak TFLOPS | Efficiency |
|---|---|---|---|
| FP8 | 8 | 5050.0 | 6.733 TFLOPS/W |
| FP4 | 4 | 10100.0 | 13.467 TFLOPS/W |
| BF16 | 16 | 1262.5 | 1.683 TFLOPS/W |
Power Specifications
TDP
750 W
Max Power
862 W
Power Connector
PCIe 16-pin
Cooling
Air or liquid cooled, second-generation closed-loop liquid cooling heat exchanger unit
Memory Specifications
Capacity
216 GB
Type
HBM3e
Bandwidth
7000 GB/s
Interface
--
Hardware & Design
Form Factor
Custom
Architecture
Maia 200
Process Node
TSMC N3
Launch Year
2026
Variant
Standard
Market Segment
Professional
Transistors
140.0 billion
Full Specifications
| Chip Design | |
|---|---|
| Transistors | 140.0 billion |
| Process Node | TSMC N3 |
| Memory | |
| VRAM | 216 GB |
| Memory Type | HBM3e |
| Bandwidth | 7.0 TB/s |
| On-Die SRAM | 272 MB |
| Interconnect & I/O | |
| GPU-to-GPU | Ethernet scale-up (Maia AI Transport Layer) |
| Interconnect Bandwidth | 2.8 TB/s |
| Power & Thermal | |
| TDP | 750 W |
| Cooling | Air or liquid cooled, second-generation closed-loop liquid cooling heat exchanger unit |
| Enterprise Features | |
| Compute APIs | PyTorch, Triton, Maia SDK, NPL, MCCL |
| General | |
| Form Factor | Custom |
| Architecture | Maia 200 |
| Launch Year | 2026 |
Documentation & Resources
Common Use Cases
The Microsoft Maia 200 is optimized for high-performance computing tasks with Maia 200 architecture delivering high TFLOPS of compute power.
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