NVIDIA GPU Architectures Explained
Understanding the Evolution from Pascal to Blackwell
NVIDIA's GPU architectures represent major technology platforms that define entire generations of products. Each architecture introduces fundamental innovations in processing capabilities, memory systems, and specialized AI acceleration—spanning from consumer graphics cards to datacenter supercomputers.
Understanding the difference between an architecture (like Hopper), a product (like H100), and a system (like Grace Hopper Superchip) is essential for making informed decisions about GPU infrastructure. This guide breaks down NVIDIA's naming conventions, explains key concepts like Tensor Cores and NVLink, and traces the evolution from Kepler (2012) to today's cutting-edge Blackwell architecture.
What You'll Learn
- How to decode NVIDIA's naming system (Architecture vs. Product vs. Superchip)
- Key innovations in each architecture generation
- Essential concepts: Tensor Cores, multi-die designs, NVLink, and Transformer Engine
- Side-by-side technical comparisons across all datacenter architectures
Decoding NVIDIA's Naming
Architecture vs Product vs Superchip — here's the difference in plain English
Architecture
The blueprint defining a GPU family's core technology and capabilities
Product
A specific GPU model built on an architecture — one arch, many products
Superchip
CPU + GPU unified with ultra-fast interconnects for seamless data sharing
GPU Architecture Evolution Timeline
Click on any architecture to learn more
Essential GPU Concepts
The building blocks that make modern AI acceleration possible
What is a Superchip?
A superchip combines different processor types (CPU + GPU) into one unified system.
NVIDIA Superchips like Grace Hopper integrate an ARM-based Grace CPU with a Hopper GPU using high-bandwidth NVLink-C2C interconnects. This creates a unified memory architecture where CPU and GPU can access the same memory space with 900GB/s bandwidth - 7x faster than PCIe Gen5. This eliminates memory copy overhead and enables seamless data sharing between processors.
What are Tensor Cores?
Specialized hardware units optimized for matrix operations in AI workloads.
Tensor Cores are specialized processing units designed to accelerate matrix multiplication operations fundamental to deep learning. Each generation adds new capabilities: Gen 1 (Volta) introduced FP16, Gen 2 (Turing) added INT8, Gen 3 (Ampere) brought TF32 and structural sparsity, Gen 4 (Hopper/Ada) added FP8 and Transformer Engine, and Gen 5 (Blackwell) introduced FP4 precision. They deliver 10-20x speedup over CUDA cores for AI training and inference.
Multi-Die GPU Architecture
Using multiple silicon dies connected together to create one massive GPU.
Modern chip manufacturing has physical size limits (reticle limit). Multi-die architecture overcomes this by connecting 2+ GPU dies via ultra-fast interconnects, making them appear as a single GPU to software. Blackwell pioneered this with its 2-die design reaching 208B transistors - impossible in a single die. The interconnect bandwidth must be extremely high to avoid bottlenecks between dies.
NVLink: GPU-to-GPU Interconnect
High-speed interconnect for direct GPU-to-GPU communication.
NVLink is NVIDIA's proprietary high-bandwidth, low-latency interconnect for multi-GPU systems. It allows GPUs to directly share memory and communicate without going through the CPU or PCIe bus. NVLink bandwidth has evolved: Gen 1 (Pascal) at 160GB/s, Gen 2 (Volta) at 300GB/s, Gen 3 (Ampere) at 600GB/s, Gen 4 (Hopper) at 900GB/s, and Gen 5 (Blackwell) at 1800GB/s. Essential for training large models across multiple GPUs.
Explore NVIDIA Architectures
Click any architecture to dive deep into specs, benchmarks, and GPU models
Apple M5
2025
Blackwell Ultra
2025
Enhanced variant of Blackwell architecture featuring increased HBM capacity (288GB) and improved FP4 performance for the most demanding AI workloads.
Apple M4
2024
Fourth-generation Apple Silicon SoC on second-gen 3nm process. Enhanced GPU performance and power efficiency with LPDDR5X support.
Blackwell
2024
Next-generation 2-die GPU architecture with 208B transistors, 5th-gen Tensor Cores supporting FP4 precision, and breakthrough AI inference performance.
Apple M3
2023
Third-generation Apple Silicon SoC built on TSMC 3nm process. Features Dynamic Caching, hardware-accelerated ray tracing, and mesh shading.
Apple M2
2022
Second-generation Apple Silicon SoC. Up to 10-core GPU with improved performance per watt and higher memory bandwidth.
Hopper
2022
Fourth-generation datacenter GPU architecture featuring Transformer Engine, 4th-gen Tensor Cores with FP8 support, and enhanced NVLink for AI training and HPC workloads.
Apple M1
2020
First-generation Apple Silicon SoC. 8-core GPU based on Apple's custom GPU architecture with unified memory.
Side-by-Side Comparison
Compare specs, performance, and innovations across all architectures
| Architecture | Use Case | Process | Tensor Core Gen | Max HBM | Key Innovation | |||
|---|---|---|---|---|---|---|---|---|
| Apple M5 | 2025 | consumer | 3nm | — | — | — | — | — |
| Blackwell Ultra 2-die | 2025 | datacenter | TSMC 4NP | 208B | Gen 5 | 288 GB | 1.4KW | Enhanced Blackwell with 288GB HBM3e |
| Apple M4 | 2024 | consumer | 3nm | — | — | — | — | — |
| Blackwell 2-die | 2024 | datacenter | TSMC 4NP | 208B | Gen 5 | 192 GB | 1.2KW | First 2-die GPU design with FP4 precision |
| Apple M3 | 2023 | consumer | 3nm | — | — | — | — | — |
| Apple M2 | 2022 | consumer | 5nm | — | — | — | — | — |
| Hopper | 2022 | datacenter | TSMC 4N | 80B | Gen 4 | 141 GB | 700W | Transformer Engine with FP8 precision |
| Apple M1 | 2020 | consumer | 5nm | — | — | — | — | — |
Common Questions
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