NVIDIA GPU Architectures Explained

CDNA 6 is the sixth generation of AMD's data center compute architecture, named by AMD at CES 2026 and scheduled to arrive with the Instinct MI500 Series in 2027. AMD has stated three things about it and no more: it is built on an advanced 2nm process, it uses HBM4E memory, and it succeeds the CDNA 5 architecture that debuted with the Instinct MI400 series in 2026. AMD has published no compute unit count, no clock speed, no transistor count, no memory capacity or bandwidth, no board power and no throughput figure at any precision for any CDNA 6 part. Its single performance claim is a projection that an MI500-powered AI rack will deliver up to a thousand times the AI performance of an MI300X platform, a comparison AMD makes between a rack and a platform without naming a precision on either side, and which therefore cannot be reduced to a per-accelerator figure. CDNA 6 silicon will power the AMD Helios 500 rack-scale system alongside EPYC "Verano" CPUs and Pensando "Como" and "Monza" networking, and AMD has already named its successor, the MI600 Series in the Helios 600 rack.

Fifth generation AMD CDNA architecture, introduced with the Instinct MI400 series in 2026. CDNA 5 moves the compute front end to Work Group Processors with Wave32 execution, stacks 3D hybrid bonded compute dies on a CoWoS-L package, and splits the design into eight TSMC N2 Accelerator Complex Dies plus two I/O dies and two Fabric and Cache dies on N3. It is the first Instinct generation on HBM4 and the first to use UALink over Ethernet for rack scale-up, and it quadruples dense OCP MXFP4 and MXFP8 matrix throughput per GPU versus CDNA 4.

Da Vinci v3

2026

datacenter

Da Vinci v3 is the Ascend 950 generation and the first Huawei architecture with native FP8 and 4-bit compute. It is also the first split into two memory-specialised parts: the Ascend 950PR pairs 128 GB of Huawei's own HiBL 1.0 at 1,600 GB/s for prefill and recommendation work, while the Ascend 950DT pairs 144 GB of HiZQ 2.0 at 4,000 GB/s for decode. Both carry 2,000 GB/s of Unified Bus 2.0 scale-up. The Atlas 350 accelerator card is built on the 950PR chip as a de-rated bin, at seven eighths of its memory and bandwidth. Huawei has published no process node, transistor count or die size for this generation, and the parts are export-controlled to the Chinese domestic market.

Dragonfly

2026

datacenter

Dragonfly is Qualcomm's brand for its data center AI silicon, introduced with the AI200 and AI250 rack-scale inference accelerators announced on 27 October 2025 and extended by a third-generation AI300 on Qualcomm's published annual cadence. Its defining decision is memory: Dragonfly accelerators carry LPDDR rather than HBM, reaching 768 GB per card where contemporary HBM parts reach 144 GB to 432 GB, and accepting far lower bandwidth in exchange for capacity, cost and supply availability. The design target is large-model inference economics rather than peak throughput, and Qualcomm markets it on total cost of ownership and performance per dollar per watt rather than on FLOPS. Qualcomm builds on its NPU heritage from the Cloud AI 100 family and Snapdragon, but has published no microarchitecture name, no NPU generation number, no AI-core count, no clock speed, no process node and no throughput figure of any kind for any Dragonfly part. The second-generation AI250 adds a near-memory compute architecture that Qualcomm claims delivers more than ten times the effective memory bandwidth of the AI200.

Maia 200 is Microsoft's second-generation in-house AI accelerator architecture and its first silicon and system platform built specifically for inference rather than training. Compute is organised as a hierarchy: a tile pairs a Tile Tensor Unit for matrix multiply with a Tile Vector Processor for programmable SIMD work, backed by multi-banked Tile SRAM, a tile DMA engine and a lightweight Tile Control Processor; tiles compose into clusters that share a large Cluster SRAM and a cluster DMA subsystem staging traffic to co-packaged HBM; clusters compose into the SoC. Both SRAM tiers are fully software managed, so compilers and kernels pin working sets on die rather than relying on cache heuristics, and tile and SRAM redundancy schemes are built in for yield. The Tile Tensor Unit is optimised for FP8, FP6 and FP4 matrix multiplication including mixed FP8 activations against FP4 weights, with hardware casting between storage and compute types at line rate. Scale-up is Ethernet rather than a proprietary fabric: an on-die NIC provides 1.4 TB/s unidirectional bandwidth, Microsoft's AI Transport Layer protocol adds packet spraying, multipath routing and congestion-resistant flow control, groups of four accelerators form a switchless Fully Connected Quad, and a switched second tier extends the domain to 6,144 accelerators.

Rubin is NVIDIA's datacenter GPU architecture for 2026, succeeding Blackwell and Blackwell Ultra and named after the astronomer Vera Rubin. A Rubin GPU is a 336 billion transistor part built from two reticle-limited compute dies joined by the NVIDIA High-Bandwidth Interface, carrying 224 streaming multiprocessors and 896 Tensor Cores, paired with 288 GB of HBM4 at 22 TB/s and connected by sixth-generation NVLink at 3.6 TB/s per GPU. It pairs with the 88-core Vera CPU over NVLink-C2C to form the Vera Rubin Superchip, and 72 GPUs with 36 CPUs form the Vera Rubin NVL72 rack. Rubin introduces NVFP4, a microscaled four-bit format with block-level scaling, and a third-generation Transformer Engine with hardware-accelerated adaptive compression. It is also the first NVIDIA architecture to offer both native and Tensor Core emulated FP32 and FP64, so an SGEMM or DGEMM workload sees roughly three and six times the native ALU throughput respectively. The generation also included Rubin CPX, a monolithic GDDR7 part for the context phase of long-context inference, which NVIDIA removed from its roadmap at GTC 2026, and is followed in 2027 by Rubin Ultra.

Xe3P is the performance-optimised variant of Intel's Xe3 graphics architecture. Its first announced datacenter application is Crescent Island, an inference accelerator that pairs Xe3P with LPDDR5X rather than HBM in order to reach very large memory capacity in a 350 W air-cooled PCIe card. Intel has described the datatype range as spanning native FP4 and MXFP4 microscaling formats through to FP64, but has published no throughput, clock, core count or process node figures for any Xe3P part.

Enhanced variant of Blackwell architecture featuring increased HBM capacity (288GB) and improved FP4 performance for the most demanding AI workloads.

XCORE 1.5

2025

datacenter

XCORE 1.5 is the second generation of MetaX's compute GPU IP, named as such in the company's STAR Market filing, and this database holds it as the C600. The part moves the line to HBM3e and an OAM module: 144 GB and up to 1,000 W, with MetaXLink for scale-up. That capacity is a press-corroborated figure sitting inside MetaX's own published floor of more than 96 GB, and it is flagged as such on the GPU row rather than presented as a datasheet value. Memory bandwidth, process node and throughput figures are all unpublished, and a widely circulated set of C600 numbers is disqualified because its power figure contradicts MetaX's own.

XCORE 2.5

2025

datacenter

XCORE 2.5 is the third generation of MetaX's compute GPU instruction set, named in the company's STAR Market filing as the successor built on the XCORE 1.5 of the C600. This database holds it as the C700, and every numeric column on both rows is empty because MetaX has published nothing: no throughput at any precision, no memory capacity, type or bandwidth, no power figure, no process node and no interconnect. At the date of the filing the project was in physical implementation and the chip had not been manufactured. The widely repeated claim that the C700 approaches an H100 is a qualitative positioning sentence in an IPO document with no number attached, and nothing here derives from it. Two naming traps: XCORE 2.0 is MetaX's RENDER instruction set and is not the compute successor to XCORE 1.5, and MetaX never writes C700 and XCORE 2.5 in the same sentence, so the pairing is an identification from the company's own ISA ladder rather than a MetaX label. The year on both rows is the disclosure year, not a launch year.

Fourth-generation Apple Silicon SoC on second-gen 3nm process. Enhanced GPU performance and power efficiency with LPDDR5X support.

Next-generation 2-die GPU architecture with 208B transistors, 5th-gen Tensor Cores supporting FP4 precision, and breakthrough AI inference performance.

Third-generation Apple Silicon SoC built on TSMC 3nm process. Features Dynamic Caching, hardware-accelerated ray tracing, and mesh shading.

Cloud AI 100

2023

datacenter

Cloud AI 100 is Qualcomm's first data center AI architecture, a fixed-function inference design built on a 7 nm process and sold as PCIe cards rather than as a rack-scale system. Its defining choice is on-die memory: each AI core owns 9 MB of software-managed SRAM, giving 576 MB on the largest card, which is more local scratchpad memory than any other non-wafer-scale accelerator carries and which lets inference workloads avoid DRAM traffic entirely for many layers. Capacity comes from LPDDR4x rather than HBM, trading bandwidth for cost and power in a 150 W envelope. Qualcomm publishes throughput for exactly two datatypes, INT8 and FP16, and no architectural detail beyond the AI core count and its SRAM allocation: there is no published clock speed, no MAC width, no die size and no transistor count for any part in the family. The line spans five SKUs cut from the same core, differing in how many cores are enabled and at what clock, from a 16-core 75 W card to a 64-core 150 W card. Qualcomm has never applied its later Dragonfly data center brand to this family, and never uses the word Hexagon in any Cloud AI 100 document. It remains the only Qualcomm data center accelerator that has shipped and can be rented, its Dragonfly successors having been announced with no published throughput figures and no availability.

MTIA

2023

datacenter

MTIA, the Meta Training and Inference Accelerator, is Meta's family of in-house AI accelerators, developed in close partnership with Broadcom and deployed only inside Meta's own data centers. The architecture is organised around a grid of processing elements. Each PE contains two RISC-V vector cores, a Dot Product Engine for matrix multiplication, a Special Function Unit for activations and elementwise operations, a Reduction Engine for accumulation and inter-PE communication, and a DMA engine feeding local scratch memory. Chips are assembled from modular chiplets, which is what lets Meta ship a new generation on a roughly six-month cadence rather than a two-year one: MTIA 300 uses one compute chiplet with two network chiplets, MTIA 400 combines two compute chiplets to double compute density, and MTIA 500 moves to a two-by-two arrangement of smaller compute chiplets surrounded by HBM stacks, two network chiplets and an SoC chiplet providing PCIe connectivity to the host. The design philosophy is explicitly inference-first and cost-driven rather than peak-FLOPS driven, with built-in NIC chiplets, dedicated message engines that offload communication collectives, and near-memory compute for reduction-based collectives. Later generations add hardware acceleration for attention and mixture-of-experts bottlenecks and custom low-precision data types intended to raise throughput without hurting model quality. Across the generation Meta states that HBM bandwidth rises 4.5 times and compute rises 25 times, though that 25x figure compares MTIA 300 at 8-bit precision with MTIA 500 at 4-bit precision rather than measuring like for like. Software is PyTorch native, with a graph compiler, a Triton compiler and eager-mode runtime support, which Meta treats as central to getting internal workloads onto the hardware quickly.

Second-generation Apple Silicon SoC. Up to 10-core GPU with improved performance per watt and higher memory bandwidth.

Biren SPC

2022

datacenter

Biren SPC is Biren Technology's first-generation general-purpose GPU architecture. The name is a label used by this database rather than a Biren one: the company calls it simply its first-generation GPGPU architecture and has never given it a name. The specified part is the BR100, presented at Hot Chips 2022 and for a while the most ambitious Chinese datacenter GPU design published anywhere: a 64 GB HBM2e OAM module at 1,600 GB/s and 550 W, rated at 256 TFLOPS FP32, 512 TFLOPS TF32, 1,024 TFLOPS BF16 and 2,048 TOPS INT8, with 2,300 GB/s of BLink scale-up bandwidth. Those figures come from Biren's own conference presentation rather than a datasheet, so they are recorded as a vendor claim. The inference-oriented BR110 shares this architecture and is also held here, but with no specifications at all: Biren has never published a single throughput, memory, power or process figure for it, and nothing on that row is inherited from the BR100. Read the generation in its commercial context, which is the largest fact about it: Biren has been under US export restrictions since October 2023, which cut it off from leading-edge foundry capacity, so shipped volume is very much smaller than the specification implies.

Fourth-generation datacenter GPU architecture featuring Transformer Engine, 4th-gen Tensor Cores with FP8 support, and enhanced NVLink for AI training and HPC workloads.

First-generation Apple Silicon SoC. 8-core GPU based on Apple's custom GPU architecture with unified memory.

Da Vinci

2018

datacenter

Da Vinci is Huawei's NPU core architecture, used across the whole Ascend line from edge parts to datacenter training accelerators. Its compute core combines a 3D Cube matrix unit with vector and scalar units, the Cube being the direct architectural analogue of an NVIDIA Tensor Core or an AMD Matrix Core, and every matrix-format throughput figure this database records for an Ascend part is a Cube figure. The first generation is the Ascend 910A, built on TSMC 7nm with 32 GB of HBM2 at 1,228 GB/s and a 310 W envelope. Later generations moved to SMIC after export controls closed TSMC to Huawei. Software is CANN and MindSpore rather than CUDA.