Huawei Ascend 910A
Overview
Huawei Ascend 910 (retroactively referred to as 910A after the 910B/910C launches) is Huawei's first-generation Da Vinci datacenter AI accelerator, launched in 2019 on TSMC's 7nm process. The chip packs 32 Da Vinci AI cores and delivers 256 TFLOPS FP16 / 512 TOPS INT8, paired with 32 GB HBM2 at 1.2 TB/s. It ships in the Atlas 800 server and Atlas 300T accelerator card, with 720 Gbps of HCCS inter-chip bandwidth plus 2x100 Gbps RoCE for scale-out. FP32 throughput is derived as approximately 1/16 of FP16. Third-party comparison tables sometimes list 4,096 'TPP' for this chip - this is the US BIS export-control metric (FP16 TFLOPS x 16 bits), not a TFLOPS figure.
Performance
Peak theoretical throughput by precision type
| Precision | Peak |
|---|---|
FP64 | No verified data available |
FP32 32-bit floating point | 16TFLOPS |
TF32 | No verified data available |
BF16 | No verified data available |
FP16 16-bit floating point | 256TFLOPS |
FP8 | No verified data available |
FP6 | No verified data available |
FP4 | No verified data available |
INT8 8-bit integer | 512TOPS |
Dense peak divided by accelerator TDP. Board power only: excludes host CPUs, networking, cooling and facility overhead. TDP for this part: 310 W.
The Ascend 910A in the GPU landscape
Peak FP16 TFLOPS (dense) against TDP, single-GPU parts tracked by Flopper
Higher and further left is better: more half-precision throughput for less power.
Specifications
Architecture
Da Vinci
Form Factor
OAM
Launch Year
2019
Process Node
TSMC 7nm
Memory
32 GB HBM2
Bandwidth
1,228 GB/s
TDP
310 W
Max power (Flopper estimate)
~357 W est. Flopper estimate: 310 W TDP x 1.15. The vendor publishes no maximum board power for this part.
Interconnect
90 GB/s HCCS
direction and scope not stated by vendor
Spec Confidence
Official
Full Specifications
| Memory | |
|---|---|
| Memory | 32 GB |
| Memory Type | HBM2 |
| Bandwidth | 1.2 TB/s |
| Interface Width | No verified data available |
| Interconnect & I/O | |
| GPU-to-GPU | HCCS |
| Interconnect Bandwidth | 90 GB/s direction and scope not stated by vendor |
| Power & Thermal | |
| TDP | 310 W |
| Max power (Flopper estimate) | ~357 W est. |
| General | |
| Form Factor | OAM |
| Architecture | Da Vinci |
| Process Node | TSMC 7nm |
| Launch Year | 2019 |
Datasheet & Resources
Flopper Datasheet
Huawei Ascend 910A specifications, generated from our database. Printable.
Vendor product page
Huawei documentation for the Ascend 910A
Huawei AI Cluster: SuperPod and Supercluster
SemiAnalysis · 2025-09-19
Huawei Ascend Developer Documentation
CANN guides, MindSpore, Da Vinci
Data Provenance
Every figure traced to a source
Primary Source
- Publisher
- SemiAnalysis
- Published
- 2025-09-19
Data Quality
- Spec confidence
- Official
- Clock basis
- Boost
- Core precisions with figures
- 3 of 9
- Normalization
- All values in TFLOPS
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Frequently Asked Questions
How many TFLOPS does the Huawei Ascend 910A have?
The Huawei Ascend 910A delivers 16 TFLOPS FP32 and 256 TFLOPS FP16 at peak. Flopper does not currently have a verified FP8 throughput figure for it.
What is the power consumption of the Huawei Ascend 910A?
The Huawei Ascend 910A has a TDP (Thermal Design Power) rating of 310 watts.
How much memory does the Huawei Ascend 910A have?
The Huawei Ascend 910A is equipped with 32 GB of memory with 1,228 GB/s of memory bandwidth.
What architecture is the Huawei Ascend 910A based on?
The Huawei Ascend 910A is based on the Da Vinci architecture, launched in 2019.
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