Huawei Ascend 910B
Overview
The Huawei Ascend 910B is the broader-shipping second iteration of the 910 line, built on SMIC's 7nm process (N+1/N+2). Mass shipments began in 2024 with engineering samples in 2022. The mainstream B3/B4 variants deliver approximately 400 TFLOPS FP16/BF16 and 800 TOPS INT8 per chip, paired with 64 GB HBM2e at roughly 1.6 TB/s - though earlier 910B1 32 GB samples ran closer to the original 910A spec (256/256/512). The chip ships in the Atlas 800T A2 server (OAM-style module) and Atlas 300T A2 PCIe card, with reported TDP in the 350-400W range. Die measures 21.3 x 31.2 mm.
Performance
Peak theoretical throughput by precision type
| Precision | Peak |
|---|---|
FP64 | No verified data available |
FP32 | No verified data available |
TF32 | No verified data available |
BF16 Brain Float 16 | 400TFLOPS |
FP16 16-bit floating point | 400TFLOPS |
FP8 | No verified data available |
FP6 | No verified data available |
FP4 | No verified data available |
INT8 8-bit integer | 800TOPS |
Dense peak divided by accelerator TDP. Board power only: excludes host CPUs, networking, cooling and facility overhead. TDP for this part: 400 W.
The Ascend 910B in the GPU landscape
Peak FP16 TFLOPS (dense) against TDP, single-GPU parts tracked by Flopper
Higher and further left is better: more half-precision throughput for less power.
Specifications
Architecture
Da Vinci v2
Form Factor
OAM
Launch Year
2024
Process Node
SMIC 7nm
Memory
64 GB HBM2e
Bandwidth
1,600 GB/s
TDP
400 W
Max power (Flopper estimate)
~460 W est. Flopper estimate: 400 W TDP x 1.15. The vendor publishes no maximum board power for this part.
Interconnect
392 GB/s HCCS
direction and scope not stated by vendor
Spec Confidence
Vendor claimed
Full Specifications
| Memory | |
|---|---|
| Memory | 64 GB |
| Memory Type | HBM2e |
| Bandwidth | 1.6 TB/s |
| Interface Width | No verified data available |
| Interconnect & I/O | |
| GPU-to-GPU | HCCS |
| Interconnect Bandwidth | 392 GB/s direction and scope not stated by vendor |
| Power & Thermal | |
| TDP | 400 W |
| Max power (Flopper estimate) | ~460 W est. |
| General | |
| Form Factor | OAM |
| Architecture | Da Vinci v2 |
| Process Node | SMIC 7nm |
| Launch Year | 2024 |
Datasheet & Resources
Flopper Datasheet
Huawei Ascend 910B specifications, generated from our database. Printable.
China's AI Chip Ecosystem
CSET Georgetown · 2024-06-01
Huawei Ascend Developer Documentation
CANN guides, MindSpore, Da Vinci
Data Provenance
Every figure traced to a source
Primary Source
- Document
- China's AI Chip Ecosystem
- Publisher
- CSET Georgetown
- Published
- 2024-06-01
Data Quality
- Spec confidence
- Vendor claimed
- Clock basis
- Boost
- Core precisions with figures
- 3 of 9
- Normalization
- All values in TFLOPS
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Browse GPU Cloud ProvidersFrequently Asked Questions
How many TFLOPS does the Huawei Ascend 910B have?
The Huawei Ascend 910B delivers 400 TFLOPS FP16 at peak. Flopper does not currently have verified FP32 and FP8 throughput figures for it.
What is the power consumption of the Huawei Ascend 910B?
The Huawei Ascend 910B has a TDP (Thermal Design Power) rating of 400 watts.
How much memory does the Huawei Ascend 910B have?
The Huawei Ascend 910B is equipped with 64 GB of memory with 1,600 GB/s of memory bandwidth.
What architecture is the Huawei Ascend 910B based on?
The Huawei Ascend 910B is based on the Da Vinci v2 architecture, launched in 2024.
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