Huawei Ascend 910C
Overview
The Huawei Ascend 910C is a dual-die package fusing two 910B-class dies on an organic substrate, mass shipping from Q1 2025. SemiAnalysis teardowns confirm 800 TFLOPS FP16 / 780 TFLOPS BF16 dense per chip, paired with 128 GB of HBM2e across 8 stacks delivering 3.2 TB/s of memory bandwidth (per Huawei Connect 2025 keynote). The chip supports FP32, HF32, FP16, BF16, and INT8 - but no native FP8 or FP4 (that arrives with the 950 generation). Scale-up bandwidth is 2,800 Gb/s over Huawei's UB (Unified Bus) fabric with 400 Gb/s of scale-out RDMA. The 910C is the foundation of the CloudMatrix 384 supercluster, where 384 chips deliver 300 PFLOPS BF16 dense across 49.2 TB of HBM at a system power of 559 kW.
Performance
Peak theoretical throughput by precision type
| Precision | Peak |
|---|---|
FP64 | No verified data available |
FP32 32-bit floating point | 50TFLOPS |
TF32 | No verified data available |
BF16 Brain Float 16 | 800TFLOPS |
FP16 16-bit floating point | 800TFLOPS |
FP8 | No verified data available |
FP6 | No verified data available |
FP4 | No verified data available |
INT8 8-bit integer | 1,600TOPS |
Dense peak divided by accelerator TDP. Board power only: excludes host CPUs, networking, cooling and facility overhead. TDP for this part: 600 W.
The Ascend 910C in the GPU landscape
Peak FP16 TFLOPS (dense) against TDP, single-GPU parts tracked by Flopper
Higher and further left is better: more half-precision throughput for less power.
Specifications
Architecture
Da Vinci v2 (dual-die)
Form Factor
OAM
Launch Year
2025
Process Node
SMIC 7nm
Memory
128 GB HBM2e
Bandwidth
3,200 GB/s
TDP
600 W
Max power (Flopper estimate)
~690 W est. Flopper estimate: 600 W TDP x 1.15. The vendor publishes no maximum board power for this part.
Interconnect
350 GB/s Unified Bus (UB)
direction and scope not stated by vendor
Spec Confidence
Official
Full Specifications
| Memory | |
|---|---|
| Memory | 128 GB |
| Memory Type | HBM2e |
| Bandwidth | 3.2 TB/s |
| Interface Width | No verified data available |
| Interconnect & I/O | |
| GPU-to-GPU | Unified Bus (UB) |
| Interconnect Bandwidth | 350 GB/s direction and scope not stated by vendor |
| Power & Thermal | |
| TDP | 600 W |
| Max power (Flopper estimate) | ~690 W est. |
| General | |
| Form Factor | OAM |
| Architecture | Da Vinci v2 (dual-die) |
| Process Node | SMIC 7nm |
| Launch Year | 2025 |
Datasheet & Resources
Flopper Datasheet
Huawei Ascend 910C specifications, generated from our database. Printable.
Vendor product page
Huawei documentation for the Ascend 910C
Huawei AI Cluster: SuperPod and Supercluster
SemiAnalysis · 2025-09-19
Huawei Ascend Developer Documentation
CANN guides, MindSpore, Da Vinci
Data Provenance
Every figure traced to a source
Primary Source
- Publisher
- SemiAnalysis
- Published
- 2025-09-19
Data Quality
- Spec confidence
- Official
- Clock basis
- Boost
- Core precisions with figures
- 4 of 9
- Normalization
- All values in TFLOPS
Compare cloud providers offering on-demand GPU instances for AI training, inference, and HPC workloads.
Browse GPU Cloud ProvidersSystems Using This GPU
Pre-configured systems featuring the Huawei Ascend 910C
| System | GPU Count | Peak Performance | Total Power | |
|---|---|---|---|---|
Huawei Atlas 800I A3 Atlas · rack · 2025 | 8x Ascend 910C | 4.48 PFLOPS | 14.6 kW | View System |
Huawei Atlas 800T A3 Atlas · rack · 2025 | 8x Ascend 910C | 6.00 PFLOPS | No verified data available | View System |
Huawei Atlas 900 A3 SuperPoD Atlas · pod · 2025 | 384x Ascend 910C | 614 PFLOPS | No verified data available | View System |
Frequently Asked Questions
How many TFLOPS does the Huawei Ascend 910C have?
The Huawei Ascend 910C delivers 50 TFLOPS FP32 and 800 TFLOPS FP16 at peak. Flopper does not currently have a verified FP8 throughput figure for it.
What is the power consumption of the Huawei Ascend 910C?
The Huawei Ascend 910C has a TDP (Thermal Design Power) rating of 600 watts.
How much memory does the Huawei Ascend 910C have?
The Huawei Ascend 910C is equipped with 128 GB of memory with 3,200 GB/s of memory bandwidth.
What architecture is the Huawei Ascend 910C based on?
The Huawei Ascend 910C is based on the Da Vinci v2 (dual-die) architecture, launched in 2025.
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