Roadmap chip — Huawei Connect 2025 announcement, not yet shipping
HU
Huawei Ascend 960
Da Vinci v4 (chiplet) OAM 2027
VRAM
288 GB
Bandwidth
9.6 TB/s
memory
Performance Metrics
Peak theoretical throughput by precision type
| Precision | Bits | Peak TFLOPS | |
|---|---|---|---|
| FP8 | 8 | 2000.0 | |
| FP4 | 4 | 4000.0 | |
| FP16 | 16 | 1000.0 | |
| BF16 | 16 | 1000.0 |
Power Specifications
TDP
--
Max Power
--
Power Connector
PCIe Slot
Cooling
Air
Memory Specifications
Capacity
288 GB
Type
--
Bandwidth
9600 GB/s
Interface
--
Hardware & Design
Form Factor
OAM
Architecture
Da Vinci v4 (chiplet)
Process Node
--
Launch Year
2027
Variant
Standard
Market Segment
Data Center
Full Specifications
| Memory | |
|---|---|
| VRAM | 288 GB |
| Bandwidth | 9.6 TB/s |
| Interconnect & I/O | |
| GPU-to-GPU | Unified Bus 2.0 |
| Interconnect Bandwidth | 2.2 TB/s |
| Power & Thermal | |
| General | |
| Form Factor | OAM |
| Architecture | Da Vinci v4 (chiplet) |
| Launch Year | 2027 |
Documentation & Resources
Common Use Cases
General Compute AI/ML Workloads Data Processing
The Huawei Ascend 960 is optimized for high-performance computing tasks with Da Vinci v4 (chiplet) architecture delivering high TFLOPS of compute power.
Where to Rent
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