Huawei Ascend 960
Overview
Roadmap chip announced at Huawei Connect 2025 (September 2025). Specs based on Huawei's public roadmap disclosure; not yet shipping. The Ascend 960 is Huawei's first chiplet-style design (Blackwell-style, vs the Hopper-style monolithic-pair 910C/950) and targets a Q4 2027 launch. It doubles 950-generation throughput to 2 PFLOPS FP8 / 4 PFLOPS FP4, paired with 288 GB of memory at 9.6 TB/s and 2.2 TB/s of scale-up interconnect. The 960 introduces HiF4, Huawei's proprietary 4-bit format claimed to be more accurate than industry-standard MXFP4. Memory type and TDP have not yet been disclosed.
Performance
Peak theoretical throughput by precision type
| Precision | Peak |
|---|---|
FP64 | No verified data available |
FP32 | No verified data available |
TF32 | No verified data available |
BF16 Brain Float 16 | 1,000TFLOPS |
FP16 16-bit floating point | 1,000TFLOPS |
FP8 8-bit floating point | 2,000TFLOPS |
FP6 | No verified data available |
FP4 4-bit floating point | 4,000TFLOPS |
INT8 | No verified data available |
Specifications
Architecture
Da Vinci v4 (chiplet)
Form Factor
OAM
Launch Year
2027
Process Node
No verified data available
Memory
288 GB
Bandwidth
9,600 GB/s
TDP
No verified data available
Max power
No verified data available
Interconnect
2.2 TB/s Unified Bus 2.0
direction and scope not stated by vendor
Spec Confidence
Vendor claimed
Full Specifications
| Memory | |
|---|---|
| Memory | 288 GB |
| Memory Type | No verified data available |
| Bandwidth | 9.6 TB/s |
| Interface Width | No verified data available |
| Interconnect & I/O | |
| GPU-to-GPU | Unified Bus 2.0 |
| Interconnect Bandwidth | 2.2 TB/s direction and scope not stated by vendor |
| Power & Thermal | |
| TDP | No verified data available |
| Max power | No verified data available |
| General | |
| Form Factor | OAM |
| Architecture | Da Vinci v4 (chiplet) |
| Process Node | No verified data available |
| Launch Year | 2027 |
Datasheet & Resources
Flopper Datasheet
Huawei Ascend 960 specifications, generated from our database. Printable.
Huawei details its AI chip roadmap through 2028
Tom's Hardware · 2025-09-19
Huawei Ascend Developer Documentation
CANN guides, MindSpore, Da Vinci
Data Provenance
Every figure traced to a source
Primary Source
- Publisher
- Tom's Hardware
- Published
- 2025-09-19
Data Quality
- Spec confidence
- Vendor claimed
- Clock basis
- Boost
- Core precisions with figures
- 4 of 9
- Normalization
- All values in TFLOPS
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Browse GPU Cloud ProvidersFrequently Asked Questions
How many TFLOPS does the Huawei Ascend 960 have?
The Huawei Ascend 960 delivers 1,000 TFLOPS FP16 and 2,000 TFLOPS FP8 at peak. Flopper does not currently have a verified FP32 throughput figure for it.
What is the power consumption of the Huawei Ascend 960?
Flopper does not currently have a verified TDP (Thermal Design Power) figure for the Huawei Ascend 960.
How much memory does the Huawei Ascend 960 have?
The Huawei Ascend 960 is equipped with 288 GB of memory with 9,600 GB/s of memory bandwidth.
What architecture is the Huawei Ascend 960 based on?
The Huawei Ascend 960 is based on the Da Vinci v4 (chiplet) architecture, launched in 2027.
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