Meta MTIA 300

The Meta MTIA 300 is the third generation of Meta's in-house Training and Inference Accelerator and the first of four chips Meta detailed in March 2026. It was designed for ranking and recommendation workloads, the dominant Meta workload before generative AI took off, and it is in production for R&R training. It pairs 216 GB of HBM at 6.1 TB/s with a module power budget of 800 W, and delivers 1.2 PFLOPS of FP8 and 0.6 PFLOPS of BF16. It has no MX4 datapath, which is the main capability gap against its successors. The chip is built from one compute chiplet and two network chiplets alongside several HBM stacks, with the compute chiplet holding a grid of processing elements, each containing two RISC-V vector cores, a Dot Product Engine for matrix multiplication, a Special Function Unit, a Reduction Engine and a DMA engine. Its distinguishing features against earlier MTIA parts are built-in NIC chiplets, dedicated message engines that offload communication collectives, and near-memory compute for reduction-based collectives. Those low-latency communication blocks became the foundation for the GenAI-focused chips that followed. Its scale-up domain is 16 accelerators, smaller than the 72 of later parts, which is why Meta gives it a faster 200 GB/s scale-out network to compensate.