Formerly published as MTIA v2, and then as MTIA 2i. Meta renamed the first two generations in March 2026: "MTIA 100 and MTIA 200 (formerly known as MTIA 1 and MTIA 2i)". CAPTIVE SILICON. Meta does not sell, rent or cloud-host MTIA, and no price exists for it at any volume. FP32 appears with no figure on purpose: Meta publishes no chip-level FP32 rate, only two per-engine SIMD rates of 2.76 TFLOPS each, and there is no published way to combine them into a figure for the chip. The INT8 rows are in TOPS despite Meta's table labelling them TFLOPS/s, which its own first-generation prose settles by calling the equivalent figure TOPS. Meta describes a rack of up to 72 of these accelerators, three chassis of twelve boards with two chips each; the figures on this row are per chip.
Meta logo

Meta MTIA 200

Type: ASICArchitecture: MTIAReleased: 2024Process: 5nmSpec confidence: Official
Memory
128 GB
LPDDR5
Bandwidth
205 GB/s
memory
TDP
90 W

Overview

MTIA 200 is the same 8x8 grid of processing elements as MTIA 100 rebuilt on TSMC 5nm and clocked at 1.35 GHz instead of 800 MHz, inside a 90 W envelope instead of 25 W. The result is 354 TOPS of dense INT8 and 177 TFLOPS of dense FP16 or BF16, roughly three and a half times the first generation, with the memory grown to match: 256 MB of on-chip SRAM at 2.7 TB/s and 128 GB of LPDDR5 at 204.8 GB/s. It is also the generation where Meta started labelling sparsity, publishing 708 TOPS of INT8 and 354 TFLOPS of FP16 with structured sparsity alongside the dense pair, which is why the dense and sparse columns on this row are both real published numbers rather than one of them being derived. The deployment shape changed too: rather than twelve dual M.2 cards in a general-purpose server, MTIA 200 ships in a rack of up to 72 accelerators, three chassis of twelve boards carrying two chips each. Like every MTIA generation it is captive to Meta and cannot be bought or rented.

Performance

Peak theoretical throughput by precision type

PrecisionDense2:4 Sparse
FP64
No verified data available Structured sparsity is a tensor-core feature; this vector precision has no sparse form
FP32
32-bit floating point
No verified data available Structured sparsity is a tensor-core feature; this vector precision has no sparse form
TF32
No verified data available The part supports 2:4 sparsity, but the vendor publishes no sparse figure for this precision
BF16
Brain Float 16
177TFLOPS 354TFLOPS
FP16
16-bit floating point
177TFLOPS 354TFLOPS
FP8
No verified data available The part supports 2:4 sparsity, but the vendor publishes no sparse figure for this precision
FP6
No verified data available The part supports 2:4 sparsity, but the vendor publishes no sparse figure for this precision
FP4
No verified data available The part supports 2:4 sparsity, but the vendor publishes no sparse figure for this precision
INT8
8-bit integer
354TOPS 708TOPS

The MTIA 200 in the GPU landscape

Peak FP16 TFLOPS (dense) against TDP, single-GPU parts tracked by Flopper

06001,2001,8002,4003,0000 W250 W500 W750 W1000 W1250 W1500 WInstinct MI355XMTIA 200

Higher and further left is better: more half-precision throughput for less power.

Specifications

Architecture

MTIA

Form Factor

No verified data available

Launch Year

2024

Process Node

5nm

Memory

128 GB LPDDR5

Bandwidth

204.8 GB/s

TDP

90 W

Max power (Flopper estimate)

~103 W est. Flopper estimate: 90 W TDP x 1.15. The vendor publishes no maximum board power for this part.

Processing Element

64

Spec Confidence

Official

Full Specifications

Compute Engine
Processing Element 64
Boost Clock 1.35 GHz
Chip Design
Die Size 421 mm²
Process Node 5nm
Chiplets 1 (Monolithic)
Memory
Memory 128 GB
Memory Type LPDDR5
Bandwidth 205 GB/s
Interface Width No verified data available
Effective Bandwidth 2.7 TB/s
On-Die SRAM 256 MB
Interconnect & I/O
PCIe 5.0 x8
Power & Thermal
TDP 90 W
Max power (Flopper estimate) ~103 W est.
Enterprise Features
Sparsity Yes
Compute APIs PyTorch, Triton
General
Form Factor No verified data available
Architecture MTIA
Process Node 5nm
Launch Year 2024

Datasheet & Resources

Data Provenance

Every figure traced to a source

Data Quality

Spec confidence
Official
Clock basis
Boost
Core precisions with figures
3 of 9
Normalization
All values in TFLOPS

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Frequently Asked Questions

How many TFLOPS does the Meta MTIA 200 have?

The Meta MTIA 200 delivers 177 TFLOPS FP16 at peak. Flopper does not currently have verified FP32 and FP8 throughput figures for it.

What is the power consumption of the Meta MTIA 200?

The Meta MTIA 200 has a TDP (Thermal Design Power) rating of 90 watts.

How much memory does the Meta MTIA 200 have?

The Meta MTIA 200 is equipped with 128 GB of memory with 204.8 GB/s of memory bandwidth.

What architecture is the Meta MTIA 200 based on?

The Meta MTIA 200 is based on the MTIA architecture, launched in 2024.

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