AMD Instinct MI440X OAM NEW
Overview
The AMD Instinct MI440X is the enterprise member of the MI400 series, announced by Dr. Lisa Su during the CES 2026 opening keynote on 5 January 2026. It sits between the two parts AMD has detailed: the MI455X, the frontier AI part that fills 72-GPU Helios racks, and the MI430X, the HPC and sovereign part that keeps full hardware FP64. AMD positions the MI440X for on-premises enterprise AI, powering training, fine-tuning and inference in a compact eight-GPU server built around a single EPYC "Venice" CPU, designed to drop into existing data center power and cooling rather than requiring a purpose-built AI hall. Press coverage of the CES briefing describes the MI440X and MI455X as tuned for low-precision FP4, FP8 and BF16 work while the MI430X retains FP32 and FP64, with AMD tailoring each part to a precision envelope so it can strip out redundant execution logic. AMD has published no numbers for the MI440X. It has disclosed no memory capacity or bandwidth, no board power, no process node and no throughput at any precision, so this entry deliberately carries no performance data. Specifications reported elsewhere, most often 432 GB of HBM4 at 19.6 TB/s, are the MI455X capacity paired with a bandwidth figure AMD has itself superseded, and no vendor source attributes either to the MI440X. This page will be filled in when AMD publishes a datasheet.
Performance Metrics
No performance metrics available for this GPU.
Power Specifications
TDP
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Max Power
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Power Connector
PCIe Slot
Cooling
Air
Memory Specifications
Capacity
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Type
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Bandwidth
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Interface
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Hardware & Design
Form Factor
OAM
Architecture
CDNA 5
Process Node
--
Launch Year
2026
Variant
OAM
Market Segment
Data Center
Full Specifications
| Power & Thermal | |
|---|---|
| Enterprise Features | |
| Compute APIs | ROCm |
| General | |
| Form Factor | OAM |
| Architecture | CDNA 5 |
| Launch Year | 2026 |
Documentation & Resources
Common Use Cases
The AMD Instinct MI440X is optimized for high-performance computing tasks with CDNA 5 architecture delivering high TFLOPS of compute power.
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