Sold and deployed almost entirely inside mainland China. Huawei is on the US Entity List and Ascend silicon is export-controlled wherever it is located, so it cannot be rented from any provider on this site. Superseded for new designs by the Ascend 310P. Huawei publishes no product page for the 310 chip itself: the figures here come from its own Hot Chips 31 architecture disclosure of August 2019.
HU

Huawei Ascend 310

Da Vinci SoC 2018 12nm
TDP
8 W
Da Vinci AI Core
2

Overview

The Huawei Ascend 310, codenamed Ascend-Mini, was the first Ascend processor to ship and the chip behind the entire Atlas 200 and Atlas 500 edge line. Announced by Eric Xu at Huawei Connect 2018, it pairs two Da Vinci AI cores with eight Arm Cortex-A55 host cores on a 12nm die of 104.4 square millimetres, and delivers 8 TFLOPS of FP16 or 16 TOPS of INT8 inside an 8 watt envelope, which is the efficiency point the whole design was built around. Alongside the AI cores it carries a substantial fixed-function media block, 16 channels of H.264 and H.265 decode plus one channel of encode, and an 8 MB on-chip buffer feeding the matrix units. Memory is 128-bit LPDDR4X, but capacity and bandwidth are deliberately left blank here because they are a board-level choice rather than a chip specification: Huawei's own Atlas 200 module ships the same silicon with either 4 GB or 8 GB. The Da Vinci Cube in this generation implements 4,096 FP16 MACs and 8,192 INT8 MACs and has no FP32 or BF16 matrix path at all, which is why this part carries only FP16 and INT8 figures.

Performance Metrics

Peak theoretical throughput by precision type

PrecisionBitsPeak TFLOPSEfficiency
INT8 8 16.0 2.000 TFLOPS/W
FP16 16 8.0 1.000 TFLOPS/W
FP16 Efficiency
1.000 TFLOPS/W
8.0 TFLOPS / 8W

Power Specifications

TDP

8 W

Max Power

8 W

Power Connector

PCIe Slot

Cooling

Air

Memory Specifications

Capacity

--

Type

LPDDR4X

Bandwidth

--

Interface

128-bit

Hardware & Design

Form Factor

SoC

Architecture

Da Vinci

Process Node

12nm

Launch Year

2018

Variant

Standard

Market Segment

Professional

Die Size

104 mm²

Full Specifications

Compute Engine
Da Vinci AI Core 2
Chip Design
Die Size 104 mm²
Process Node 12nm
Memory
Memory Type LPDDR4X
Interface Width 128-bit
Interconnect & I/O
PCIe 3.0 x4
Cache
L2 Cache 3 MB
Power & Thermal
TDP 8 W
Max Board Power 8 W
Enterprise Features
Compute APIs CANN, MindSpore, MindX, ACL
General
Form Factor SoC
Architecture Da Vinci
Launch Year 2018

Documentation & Resources

Common Use Cases

General Compute AI/ML Workloads Data Processing

The Huawei Ascend 310 is optimized for high-performance computing tasks with Da Vinci architecture delivering high TFLOPS of compute power.

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