HU
Huawei Ascend 950PR NEW
Da Vinci v3 OAM 2026
VRAM
128 GB
HiBL 1.0
TDP
900 W
Bandwidth
1.6 TB/s
memory
Performance Metrics
Peak theoretical throughput by precision type
| Precision | Description | Bits | Peak TFLOPS | Efficiency |
|---|---|---|---|---|
| FP8 | 8-bit floating point | 8 | 1000.0 | 1.111 TFLOPS/W |
| FP4 | 4-bit floating point | 4 | 2000.0 | 2.222 TFLOPS/W |
| FP16 | 16-bit floating point | 16 | 500.0 | 0.556 TFLOPS/W |
| BF16 | Brain Float 16 | 16 | 500.0 | 0.556 TFLOPS/W |
FP8 Efficiency
1.111 TFLOPS/W
1000.0 TFLOPS / 900W
FP16 Efficiency
0.556 TFLOPS/W
500.0 TFLOPS / 900W
Power Specifications
TDP
900 W
Max Power
1.0 kW
Power Connector
PCIe 16-pin
Cooling
Air
Memory Specifications
Capacity
128 GB
Type
HiBL 1.0
Bandwidth
1600 GB/s
Interface
--
Hardware & Design
Form Factor
OAM
Architecture
Da Vinci v3
Process Node
--
Launch Year
2026
Variant
Standard
Market Segment
Data Center
Full Specifications
| Memory | |
|---|---|
| VRAM | 128 GB |
| Memory Type | HiBL 1.0 |
| Bandwidth | 1.6 TB/s |
| Interconnect & I/O | |
| GPU-to-GPU | Unified Bus 2.0 |
| Interconnect Bandwidth | 2.0 TB/s |
| Power & Thermal | |
| TDP | 900 W |
| General | |
| Form Factor | OAM |
| Architecture | Da Vinci v3 |
| Launch Year | 2026 |
Documentation & Resources
Common Use Cases
General Compute AI/ML Workloads Data Processing
The Huawei Ascend 950PR is optimized for high-performance computing tasks with Da Vinci v3 architecture delivering high TFLOPS of compute power.
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