Apple M5 Ultra NEW
Overview
The M5 Ultra is the largest chip Apple has ever built and the first with four dies, made by joining two dual-die M5 Max chips over next-generation UltraFusion. That gives up to 80 GPU cores, each carrying its own Neural Accelerator, a 36-core CPU and a 32-core Neural Engine. For local model work the number that matters is not compute but memory: 512 GB of unified memory at 1.2 TB/s, which is more capacity than any single datacenter GPU on this site and roughly a quarter of the bandwidth of a top-end HBM part. That trade is the whole argument for a Mac Studio as an inference machine, since a model that will not fit on an 80 GB accelerator fits here comfortably and simply runs slower. Apple skipped the Ultra tier of the M4 generation altogether, so this is the first new Ultra since the M3 Ultra of March 2025, and Apple's own comparison is up to 4.3x its peak AI compute.
Performance
Peak theoretical throughput by precision type
| Precision | Peak |
|---|---|
FP64 | No verified data available |
FP32 32-bit floating point | 33TFLOPS |
TF32 | No verified data available |
BF16 | No verified data available |
FP16 | No verified data available |
FP8 | No verified data available |
FP6 | No verified data available |
FP4 | No verified data available |
INT8 | No verified data available |
Every figure here is dense. The vendor documents no structured (2:4) sparsity mode for this part, so there is no second number to quote.
Specifications
Architecture
Apple M5
Form Factor
SoC
Launch Year
2026
Process Node
3nm
Memory
512 GB LPDDR5X
Bandwidth
1,200 GB/s
TDP
No verified data available
Max Power
No verified data available
Interconnect
UltraFusion
GPU cores
80
Spec Confidence
Vendor claimed
Full Specifications
| Compute Engine | |
|---|---|
| GPU cores | 80 |
| Chip Design | |
| Process Node | 3nm |
| Chiplets | 4 (Two dual-die M5 Max chips joined by next-generation UltraFusion) |
| Memory | |
| VRAM | 512 GB |
| Memory Type | LPDDR5X |
| Bandwidth | 1.2 TB/s |
| Interface Width | No verified data available |
| Interconnect & I/O | |
| GPU-to-GPU | UltraFusion |
| Power & Thermal | |
| TDP | No verified data available |
| Max Board Power | The vendor publishes no maximum board power; the Max Power tile above estimates it from TDP |
| Enterprise Features | |
| Sparsity | No |
| General | |
| Form Factor | SoC |
| Architecture | Apple M5 |
| Process Node | 3nm |
| Launch Year | 2026 |
Datasheet & Resources
Data Provenance
Every figure traced to a source
Primary Source
- Publisher
- Apple
- Published
- 2026-08-25
Data Quality
- Spec confidence
- Vendor claimed
- Clock basis
- Boost
- Core precisions with figures
- 1 of 9
- Normalization
- All values in TFLOPS
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Frequently Asked Questions
How many TFLOPS does the Apple M5 have?
The Apple M5 delivers 33 TFLOPS FP32 at peak. Flopper does not currently have verified FP16 and FP8 throughput figures for it.
What is the power consumption of the Apple M5?
Flopper does not currently have a verified TDP (Thermal Design Power) figure for the Apple M5.
How much memory does the Apple M5 have?
The Apple M5 is equipped with 512 GB of VRAM with 1,200 GB/s of memory bandwidth.
What architecture is the Apple M5 based on?
The Apple M5 is based on the Apple M5 architecture, launched in 2026.
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