NVIDIA Groq 3 LPU

The Groq 3 LPU is the accelerator inside NVIDIA's Groq 3 LPX inference rack, and is not sold separately: it is soldered eight to a 1U tray, thirty-two trays to a rack, and there is no standalone SKU. It has no HBM, no GDDR and no hardware-managed cache hierarchy at all. Its working storage is 500 MB of on-die SRAM running at 150 TB/s, with 2.5 TB/s of chip-to-chip scale-up bandwidth, and it relies on a statically compiler-scheduled deterministic dataflow rather than caches. NVIDIA publishes 9.6 PFLOPS of FP8 per eight-LPU tray, which is 1,200 TFLOPS each, and that reconciles against the rack figure of 307.2 PFLOPS across 256 LPUs. The per-chip memory figures reconcile the same way: 256 x 500 MB is the rack's published 128 GB of SRAM, and 256 x 2.5 TB/s is its published 640 TB/s of scale-up bandwidth. Figures are dense: NVIDIA describes the matrix execution modules as providing dense multiply-accumulate capability, and a statically scheduled design has no structured-sparsity hardware, so no sparse rate exists.