SambaNova SN50 NEW

The SN50 is SambaNova's fifth-generation Reconfigurable Dataflow Unit, announced in February 2026 as a chip built for agentic inference, where many models and long contexts have to stay resident and token generation has to be fast. Like the SN40L before it, it runs a model as a dataflow pipeline laid out across the chip rather than as a sequence of kernels, and feeds it from three memory tiers: 432 MB of on-chip SRAM, 64 GB of HBM2E for active weights and hot KV cache, and a large DDR5 pool for cold caches and other models, quoted as up to 512 GB on SambaNova's product page and up to 2 TB on its datasheet. SambaNova rates it at 1,600 TFLOPS of BF16 and 3,200 TFLOPS of FP8, five times the SN40's 640 at its best format, on TSMC 5nm. SambaRacks of 16 SN50s can be joined into a scale-up domain of up to 256 chips, against 16 for the SN40L. SambaNova has published no memory bandwidth or chip power, and shipping begins in the second half of 2026.