Shipping since October 2024 but export-controlled and apparently being wound down, and Biren has published no specifications for it. Eight Biren Technology entities have been on the United States Bureau of Industry and Security Entity List since 17 October 2023 under a presumption-of-denial licensing policy, so this is a domestic-market Chinese part. Biren discloses that it adjusted the research and development direction for the BR110 during 2025 and disposed of raw materials it no longer needed, that unit sales in the first half of 2025 fell to 22 chips against 2,216 for its BR106, and its 2025 annual report does not mention the part at all, naming only the BR106 and BR166 as the chips it commercialised. The BR110 is also absent from Biren's current product catalogue. It has not been cancelled, however: it reached mass production, generated revenue, and Biren still lists it among the products its export-control disclosures cover. No performance, memory, power or process figure has ever been published for it, by Biren or anyone else, so this entry deliberately carries no specifications rather than estimates borrowed from its larger sibling.
BI

Biren BR110

Biren SPC 2024

Overview

Biren BR110 is the edge and cloud inference member of Biren Technology's first generation of general-purpose GPUs, and the quieter of the two chips built on that architecture. Biren describes it as a cost-effective, energy-efficient part designed mainly for inference at the edge, sharing its architecture with the larger BR106 while targeting embedded deployments such as industrial control systems and robotics rather than data center training. It taped out in 2022, completed post-silicon validation in 2023 and entered mass production in October 2024, shipping as a board product Biren calls the BILI 110E. Alongside multi-precision arithmetic it carries a substantial fixed-function feature set: support for up to four independent secure virtual instances, a sixteen-channel video encoder and a hundred-and-sixty-channel decoder for 1080p thirty-frame H.264 and H.265 streams, and a state-certified hardware security engine, all running on Biren's own BIRENSUPA software stack. What Biren has never published is a single engineering number. Its Hong Kong listing document, the only document in which the chip appears at all, contains no throughput figure at any precision, no memory capacity, type or bandwidth, no board power and no process node, for the BR110 or for any other Biren chip; the one hardware specification table in that document covers only BR106 and BR166 board products and omits this part entirely. The BR110 has also become hard to find. It appears nowhere on Biren's website, whose current catalogue lists five products built on the BR106 and BR166, and nowhere in the 2025 annual report, which names only those two chips as commercialised. Biren's own accounts explain part of the reason, recording an adjustment in the research and development direction for the BR110 during 2025 and the disposal of raw materials that were no longer required, with first-half 2025 unit sales of twenty-two chips against more than two thousand for the BR106. The company continues to name it in its export-control disclosures, so it remains a live product rather than a cancelled one, but the commercial centre of gravity has clearly moved to the BR106 and BR166 lines and to the second-generation BR20X series that Biren has said will add dedicated FP8 and FP4 engines.

Performance Metrics

No performance metrics available for this GPU.

Power Specifications

TDP

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Max Power

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Power Connector

PCIe Slot

Cooling

Air

Memory Specifications

Capacity

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Type

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Bandwidth

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Interface

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Hardware & Design

Form Factor

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Architecture

Biren SPC

Process Node

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Launch Year

2024

Variant

Standard

Market Segment

Professional

Full Specifications

Power & Thermal
Enterprise Features
Compute APIs BIRENSUPA
General
Architecture Biren SPC
Launch Year 2024

Documentation & Resources

Common Use Cases

General Compute AI/ML Workloads Data Processing

The Biren BR110 is optimized for high-performance computing tasks with Biren SPC architecture delivering high TFLOPS of compute power.

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