Sold and deployed almost entirely inside mainland China. Huawei is on the US Entity List and Ascend silicon is export-controlled wherever it is located, so it cannot be rented from any provider on this site.
HU

Huawei Atlas 300V

Da Vinci PCIe 2022
VRAM
24 GB
LPDDR4X
TDP
72 W
Bandwidth
205 GB/s
memory

Overview

The Huawei Atlas 300V is a video analysis card built on a down-binned Ascend 310P, rated at 100 TOPS INT8 and 50 TFLOPS FP16. Those figures are five sevenths of the 140 TOPS and 70 TFLOPS that the Atlas 300I Pro and Atlas 300V Pro achieve from the same chip at the same 72 watts, the same 204.8 GB/s of LPDDR4X bandwidth and the same board size, so this is a genuine clock or core bin rather than a rounding or transcription difference. The card pairs 24 GB of LPDDR4X with an eight-core 1.9 GHz host CPU and supports ECC, and its media block handles 80 channels of 1080p30 decode, or 10 channels of 4K60, plus 24 channels of 1080p30 encode.

Performance Metrics

Peak theoretical throughput by precision type

PrecisionBitsPeak TFLOPSEfficiency
INT8 8 100.0 1.389 TFLOPS/W
FP16 16 50.0 0.694 TFLOPS/W
FP16 Efficiency
0.694 TFLOPS/W
50.0 TFLOPS / 72W

Power Specifications

TDP

72 W

Max Power

72 W

Power Connector

PCIe Slot

Cooling

Air

Memory Specifications

Capacity

24 GB

Type

LPDDR4X

Bandwidth

204.8 GB/s

Interface

--

Hardware & Design

Form Factor

PCIe

Architecture

Da Vinci

Process Node

--

Launch Year

2022

Variant

Standard

Market Segment

Professional

Chiplets

1

Full Specifications

Chip Design
Chiplets 1
Memory
VRAM 24 GB
Memory Type LPDDR4X
Bandwidth 205 GB/s
Interconnect & I/O
PCIe 4.0 x16
Power & Thermal
TDP 72 W
Max Board Power 72 W
Enterprise Features
ECC Memory Yes
Compute APIs CANN, MindSpore, MindX, PyTorch (torch_npu), ACL
Physical & Media
Card Length 169.5 mm
General
Form Factor PCIe
Architecture Da Vinci
Launch Year 2022

Documentation & Resources

Common Use Cases

General Compute AI/ML Workloads Data Processing

The Huawei Atlas 300V is optimized for high-performance computing tasks with Da Vinci architecture delivering high TFLOPS of compute power.

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