Huawei Atlas 200I A2 20 TOPS
Overview
The Huawei Atlas 200I A2 is an edge acceleration module built on the Ascend 310B, measuring just 82 by 60 by 7 millimetres and intended to be soldered down into a customer board. This is the higher of the two bins Huawei publishes, rated at 20 TOPS INT8 and 10 TFLOPS FP16 within 25 watts. Those figures reconcile almost exactly with Huawei's own hardware documentation: a single Da Vinci V300 AI core running at 1.224 GHz across 4,096 FP16 MACs gives 10.02 TFLOPS, and the same core across 8,192 INT8 MACs gives 20.05 TOPS, a 0.3 percent agreement between a 2019 conference deck and a 2023 driver guide. The module pairs the AI core with four TaiShan V200M CPU cores at 1.6 GHz and offers LPDDR4X in 12, 8 or 4 GB configurations at 51.2, 34.1 and 34.1 GB/s respectively; note that the bandwidth ladder is not monotonic in Huawei's own table, with 8 GB and 4 GB sharing a figure. Media support is 40 channels of 1080p30 decode.
Performance Metrics
Peak theoretical throughput by precision type
| Precision | Bits | Peak TFLOPS | Efficiency |
|---|---|---|---|
| INT8 | 8 | 20.0 | 0.800 TFLOPS/W |
| FP16 | 16 | 10.0 | 0.400 TFLOPS/W |
Power Specifications
TDP
25 W
Max Power
25 W
Power Connector
PCIe Slot
Cooling
Air
Memory Specifications
Capacity
12 GB
Type
LPDDR4X
Bandwidth
51.2 GB/s
Interface
--
Hardware & Design
Form Factor
Module
Architecture
Da Vinci
Process Node
--
Launch Year
2023
Variant
20 TOPS
Market Segment
Professional
Full Specifications
| Compute Engine | |
|---|---|
| Da Vinci AI Core | 1 |
| Boost Clock | 1.22 GHz |
| Memory | |
| VRAM | 12 GB |
| Memory Type | LPDDR4X |
| Bandwidth | 51 GB/s |
| Power & Thermal | |
| TDP | 25 W |
| Max Board Power | 25 W |
| Enterprise Features | |
| Compute APIs | CANN, MindSpore, MindX, ACL |
| Physical & Media | |
| Card Length | 82 mm |
| General | |
| Form Factor | Module |
| Architecture | Da Vinci |
| Launch Year | 2023 |
Documentation & Resources
Common Use Cases
The Huawei Atlas 200I A2 is optimized for high-performance computing tasks with Da Vinci architecture delivering high TFLOPS of compute power.
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